API

Mercury

UIO

class redpitaya.drv.uio.uio(uio: str)[source]

Bases: object

UIO class provides user space access to UIO devices.

When instantiating this class the next steps are performed:

  1. The provided UIO device file is first opened.
  2. An attempt is made to exclusively lock the device file. If another process has already locked this file an error will be rised. This prevents multiple applications from accessing the same HW module.
  3. If locking is sucessfull sysfs arguments will be read to determine the maps listed in the device tree. All maps will be `mmap`ed into memory and provided as a tuple.

When an instance of uio is deleted the next steps are performed:

  1. Close all memory mappings.
  2. Close the UIO device file, which also releases the exclusive lock.
Parameters:uio (str) – device node path
uio_maps

touple of mmap objects – List of all memory maps derived from device tree node for the UIO device.

uio_mmaps

touple of mmap objects – List of all mmap-ed memory maps derived from device tree node for the UIO device.

irq_enable()[source]

Enable interrupt.

irq_disable()[source]

Disable interrupt.

irq_wait()[source]

Wait for interrupt.

pool()[source]

TODO: implement interrupt support

Events

class redpitaya.drv.evn.evn[source]

Bases: object

default()[source]

Set registers into default (power-up) state.

show_regset()[source]

Print FPGA module register set for debugging purposes.

reset()[source]

Reset state machine, is used to synchronize alwways running streams.

start()[source]

Start starte machine.

stop()[source]

Stop state machine.

trigger()[source]

Activate SW trigger.

start_trigger()[source]

Start state machine and activate SW trigger.

status_run() → bool[source]

Run status.

status_trigger() → bool[source]

Trigger status.

sync_src

Select for software event sources.

trig_src

Enable mask for hardware trigger sources.

Waveforms

class redpitaya.drv.wave.wave[source]

Bases: object

Common waveform creation.

This class provides methods for creating common waveform shapes.

sin(t: <built-in function array> = None) → <built-in function array>[source]

Sinus waveform.

Parameters:t (array_like, optional) – If not time array is provided, a default buffer sized array with a 2*PI period will be used.
Returns:waveform – Sinusoidal waveform with samples in the normalized range [-1,+1].
Return type:ndarray

References

https://docs.scipy.org/doc/numpy/reference/generated/numpy.sin.html

See also

square(), sawtooth()

square(duty: float = 0.5, t: <built-in function array> = None) → <built-in function array>[source]

Square waveform.

Parameters:
  • duty (float, optional) – Duty cycle.
  • t (array_like, optional) – If not time array is provided, a default buffer sized array with a 2*PI period will be used.
Returns:

waveform – Square waveform with samples in the normalized range [-1,+1] and given duty cycle.

Return type:

ndarray

References

http://scipy.github.io/devdocs/generated/scipy.signal.square.html

See also

sin(), sawtooth()

sawtooth(width: float = 0.5, t: <built-in function array> = None) → <built-in function array>[source]

Sawtooth waveform.

Parameters:
  • width (float, optional) – Width of rising versus the falling sawtooth edge.
  • t (array_like, optional) – If not time array is provided, a default buffer sized array with a 2*PI period will be used.
Returns:

waveform – Sawtooth waveform with samples in the normalized range [-1,+1] and given width.

Return type:

ndarray

References

http://scipy.github.io/devdocs/generated/scipy.signal.square.html

See also

sin(), square()

LED

GPIO

Analog input (XADC)

Analog output (PDM)

Hardware ID

class redpitaya.drv.hwid.hwid(uio: str = '/dev/uio/hwid')[source]

Bases: redpitaya.drv.uio.uio

Driver for hardware identification module.

hwid

int – Red Pitaya FPGA identification number (32bit).

efuse

int – Zynq FPGA efuse (57bit).

dna

int – Zynq FPGA DNA number (57bit).

gith

str – Git hash (160 bits, 40 hex characters)

.. note::

Future releases might provide access to other Zynq FPGA features.

hwid

Red Pitaya FPGA identification number.

A 32bit read only register defined at FPGA compile time.

efuse

Zynq FPGA efuse.

A 32bit value, read only for now, future versions might provide a convoluted write access scheme.

dna

Zynq FPGA DNA number.

A 57bit read-only value defined in manufacturing. Can be used as an almost unique device identification.

gith

Git hash.

A full SHA-1 hash (160 bits, 40 hex characters) for the repository from which the FPGA was built.

Generator

class redpitaya.drv.gen.gen(index: int, uio: str = '/dev/uio/gen')[source]

Bases: redpitaya.drv.evn.evn, redpitaya.drv.asg_per.asg_per, redpitaya.drv.asg_bst.asg_bst, redpitaya.drv.gen_out.gen_out, redpitaya.drv.wave.wave, redpitaya.drv.uio.uio

Generator FPGA module driver.

Module instance index should be provided

FS = 125000000.0

sampling frequency

DW = 14

data width - streaming sample

DWM = 14

data width - linear gain multiplier

DWS = 14

data width - linear offset summand

buffer_size = None

buffer size

default()[source]

Set registers into default (power-up) state.

show_regset()[source]

Print FPGA module register set for debugging purposes.

waveform

Waveworm array containing normalized values in the range [-1,1].

Array can be up to buffer_size samples in length.

class modes[source]

Bases: enum.Enum

An enumeration.

PERIODIC = 0
BURST = 1
gen.mode

Generator mode

  • ‘PERIODIC’ - continuous/periodic signals
  • ‘BURST’ - finite/infinite bursts

Oscilloscope

class redpitaya.drv.osc.osc(index: int, input_range: float, uio: str = '/dev/uio/osc')[source]

Bases: redpitaya.drv.evn.evn, redpitaya.drv.acq.acq, redpitaya.drv.osc_trg.osc_trg, redpitaya.drv.osc_fil.osc_fil, redpitaya.drv.uio.uio

Module instance index should be provided

FS = 125000000.0

sampling frequency

DW = 16

register width - linear addition multiplication

buffer_size = 16384

buffer size

CW = 31

counter size

ranges = (1.0, 20.0)

analog stage range voltages

default()[source]

Set registers into default (power-up) state.

show_regset()[source]

Print FPGA module register set for debugging purposes.

input_range

Input range can be one of the supporte ranges.

See HW board documentation for details.

sample_rate

Sample rate depending on decimation factor.

sample_period

Sample period depending on decimation factor.

pointer
data(siz: int = 16384, ptr: int = None) → <built-in function array>[source]

Data.

Parameters:
  • siz (int, optional) – Number of data samples to be read from the FPGA buffer.
  • ptr (int, optional) – End of data pointer, only use if you understand the source code.
Returns:

Array containing float samples scaled to the selected analog range. The data is alligned at the end to the last sample stored into the buffer.

Return type:

array